The present invention relates generally to wireless communication systems, and, more particularly, to physical downlink control channel processing in a wireless communication network.
A wireless communication system includes a base station and multiple user equipment devices (UEs). The UEs include both fixed and portable devices such as cellular phones, personal digital assistants (PDAs), and fixed terminals such as landline telephones and work stations that use wireless modem cards.
The base stations are base transceiver systems (BTS) that communicate with the UEs using radio-frequency (RF) signals that conform to specific standards and technologies, like long term evolution (LTE), high speed packet access (HSPA), and third generation partnership project (3GPP) standards. Each RF signal includes multiple transmission frames and each transmission frame includes multiple subframes. Each subframe further includes multiple orthogonal frequency-division multiplexing (OFDM) symbols. For example, each subframe may include two slots, where each slot further includes 7 OFDM symbols for normal cyclic prefix. Further, each subframe corresponds to 1 transmission time interval (TTI), where TTI refers to a time required by the base station for transmitting a subframe to the UE.
Based on the number of UEs in a wireless communication network and coverage area, the wireless communication network is categorized as a macro, micro, or small cell. A macro cell caters to a large number of UEs that operate in environments requiring a large coverage area such as offices and shopping centers. Small cells include pico and femto cells. A small cell caters to fewer UEs that operate a small coverage area such as a home.
A communication from the base station to the UE is referred to as downlink communication and a transmission channel used for the downlink communication is referred to as a downlink transmission channel. A communication from the UE to the base station is referred to as uplink communication and a transmission channel used for the uplink communication is referred to as an uplink transmission channel. Thus, the transmission channel includes both the downlink and uplink transmission channels, and hence, is bi-directional. The downlink transmission channel includes multiple downlink control channels that are used by the base station to configure the UEs and a physical downlink shared channel (PDSCH) that is used by the base station to transmit data to the UEs. For example, the downlink control channels may include a physical downlink control channel (PDCCH), a physical control format indicator channel (PCFICH), and a physical hybrid automatic-repeat-request indicator channel (PHICH).
During downlink communication, the base station uses the PDCCH to send control bits to a UE. The control bits include information indicative of the PDCCH and the PDSCH. Since the wireless communication network includes multiple UEs that communicate with at least one base station, the base station multiplexes the UEs in time and frequency domains on a transmission frame. The transmission frame includes multiple resource blocks (RBs) that are indicative of resources allocated to the UEs for the downlink transmission. Each RB includes multiple resource elements that are mapped to data frames to be transmitted to the UEs, and hence, RBs are associated with the data frames to be transmitted to the UEs. Thus, the base station associates the RBs with the UEs to schedule transmission of the downlink user data from the base station on the transmission frame. The base station further communicates the resource allocations to the UEs using the control bits on the PDCCH. Thus, the control bits also include information indicative of the resources allocated to the UE on a corresponding transmission channel. The control bits transmitted through the PDCCH are referred to as downlink control information (DCI).
The base station includes a power architecture system, a digital signal processing (DSP) sub-system, and a hardware accelerator. The power architecture system includes a Layer 2 (L2) processor that generates multiple DCI payloads corresponding to the multiple UEs, where each DCI payload includes a DCI corresponding to a UP. Thus, each DCI payload is user-specific and corresponds to a PDCCH corresponding to the UP. The DSP sub-system includes a Layer 1 (L1) processor. The L1 processor receives the multiple DCI payloads from the L2 processor, generates a transmission frame based on the multiple user specific DCI payloads using conventional PDCCH processing techniques, and then provides the transmission frame to the hardware accelerator for subsequent transmission.
The L1 processor processes the DCI payloads by appending a cyclic redundancy check (CRC) at the termination of each DCI payload. Subsequently, the L1 processor codes each DCI payload and executes a rate-matching algorithm to generate rate-matched coded DCI bits corresponding to each DCI payload. The rate-matched coded DCI bits corresponding to each DCI payload are also referred to as RDCI payloads or code-words.
The L1 processor multiplexes and stores the RDCI payloads for each UN in a double-data rate (DDR) buffer based on a plurality of control channel element indices (also referred to as “cceidx”) corresponding to the DCI payloads. The multiplexing of the RDCI payloads is performed by executing PDCCH multiplexing algorithm. However, during PDCCH multiplexing, unoccupied memory blocks are generated between consecutive RDCI payloads in the DDR buffer. Such unoccupied memory blocks are referred to as NIL elements. Thus, NIL elements are inserted between the multiplexed RDCI payloads in the DDR buffer.
The L1 processor executes a scrambling algorithm to utilize a scrambling sequence received from a scrambling sequence generator and scramble the entire DDR buffer. Thus, the multiplexed RDCI payloads and the NIL elements are scrambled to generate scrambled RDCI payloads and scrambled NIL elements. The scrambled RDCI payloads are referred to as SDCI payloads and scrambled NIL elements are referred to as SNIL elements.
After scrambling, quadrature phase shift keying (QPSK) modulation is used to modulate the SDCI payloads and the SNIL elements to generate modulated symbols. The modulated symbols are stored in the DDR buffer and a power boosting operation is performed on the DDR buffer.
The L1 processor executes a layer-mapping and pre-coding algorithm after the QPSK modulation to map the modulated symbols stored in the DDR buffer to antenna ports. For example, if the base station includes two antennas, the modulated symbols are divided in to first and second sets of modulated symbols. After layer-mapping and pre-coding, the L1 processor stores the first and second sets of modulated symbols in first and second temporary DDR buffers, respectively.
Next the L1 processor executes an interleaving algorithm. The L1 processor discards the modulated symbols corresponding to the SNIL elements and performs an interleaving operation on the modulated symbols corresponding to the SDCI payloads stored in the first and second temporary DDR buffers. Thus, the additional machine cycles used by the L1 processor to scramble the NIL elements, modulate the SNIL elements, layer-mapping, and pre-coding the modulated symbols corresponding to the SNIL elements are unnecessary, and increase the processing time required by the L1 processor to perform the PDCCH processing and generate the transmission frame.
The L1 processor maps the interleaved modulated symbols corresponding to the SDCI payloads to the resource element group (REG) and generates first and second sets of mapped modulated symbols by executing an REG mapping algorithm. The SDCI payloads are stored in the interleaved first and second temporary DDR buffers. The L1 processor then stores the first and second sets of mapped modulated symbols in first and second antenna buffers, respectively, for transmission.
A large number of machine cycles are consumed for interleaving and REG mapping. The L1 processor performs the interleaving operation on the modulated symbols based on interleaved locations. For REG mapping, the L1 processor processes the interleaved locations using a cyclic shifting operation to generate sequential indices. The L1 processor further stores a lookup table (LUT) having a mapping between the sequential indices and REG locations in internal memory. The L1 Processor uses the LUT to fetch a REG location based on a sequential index corresponding to a modulated symbol. Since, interleaving and REG mapping are performed independently, the L1 processor requires an excessive number of machine cycles, which increases the PDCCH processing time.
The PDCCH processing requires the L1 processor to process the DDR buffer as well as the first and second temporary DDR buffers. Therefore, the L1 processor uses many processing cycles due to the immense amount of time required to load data from the DDR buffer and store the data in the DDR buffer. The conventional PDCCH processing techniques are not cache efficient and use a lot of memory. For example, even if the DDR buffer includes only a single DCI, the L1 processor still processes the entire DDR buffer. Thus, regardless of the number of users in the wireless communication network and the size of the DCI payload, the L1 processor requires the same number of machine cycles to process the DDR buffer.
The PDCCH multiplexing algorithm does not permit the conventional PDCCH processing technique to be offloaded to multiple cores. Further, the complexity of the conventional PDCCH processing technique prevents the utilization of less complex modules such as hardware accelerators for the DCI processing.
The 3GPP standard (release-8) that corresponds to LTE provides support for 15 megahertz (MHz) and 20 MHz bandwidth. Conventionally, each TTI caters to a single user. Due to increasing numbers of UEs in small and macro cells, the base station must cater to multiple users for each TTI. For example, for the base station to cater to 64 users, it must provide support to at least 4 users per TTI. However, because conventional PDCCH processing takes so long, the base station cannot support multiple users for each TTI at higher bandwidth.
Therefore, it would be advantageous to have a wireless communication system with more efficient PDCCH processing such that it can support multiple users for each TTI.